Pongyupinpanich Surapong

Wissenschaftliche und Berufliche Ausbildung:

  • Since 2008 Doctoral Student, Institute of Microelectronic System Technische Universität Darmstadt, Germany.
  • 2000 – 2003 Master of Engineering (M.Ing) in Electrical Engineering, King Mongkut’s Institute of Technology Lardkabang, Thailand.
  • 1997 – 2000 Bachelor of Engineering (B.Ing) in Instrument Engineering, King Mongkut’s Institute of Technology Lardkabang, Thailand.

Forschungs- und Arbeitsbereiche:

  • Signal Processing: Filter Bank, Multirate System, Data Compression, and Signal Detection.
  • High Performance and High Flexibility Multiprocessor Architecture: Parallel and Pipeline Architecture.
  • Real-Time Reconfigurable System: Reconfigurable Hardware.

Veröffentlichungen:

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Betreute Vorlesungen und Praktika:

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Bachelor & Master Thesis:

  • Multirate Signal Processing for Adaptive Filter Bank implemented on FPGA: Design & Simulation on MatLab, Realization on FPGA.
  • Hardware Architecture for High-Performance Computing.
  • Pipeline and Superpipeline Execution Unit : Optimize the execution time of RISC Architecture.
  • Data Dependency for hierarchy storage : Design and analyze model dependency on each level of memory.

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02.05.2009

Offene Studien- & Diplomarbeiten, Bachelor- & Master-Theses

Hardware Architecture for High-Performance Computing

Betreuer: Pongyupinpanich Surapong

02.05.2009

Offene Studien- & Diplomarbeiten, Bachelor- & Master-Theses

Multirate Signal Processing for Adaptive Filter Bank implemented on FPGA

Design & Simulation on MatLab, Realization on FPGA.

Betreuer: Pongyupinpanich Surapong

 

Weitere Informationen:

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